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| #11 | |||||
| Administrator Join Date: Oct 2004 USA Posts: 2,548 ![]() | Hi there I've just wrote down to update our tutorial on timings to add all these math... Quote:
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Higher bandwidth is better if data is stored in subadjacent addresses. This happens because SDRAM-based memories (DDR, DDR2, etc) can deliver from the second data on with zero latency. For instance, if you would read four data that are stored side-by-side on a memory with CL5 the first data would be delivered after 5 real clock cycles but the other three data would be delivered immediately, and since DDR/DDR2/DDR3 memories deliver two data per clock cycle, each data would be delivered in half clock cycle. In other words, first data 5 clock cycles, the other three data half clock cycle each, in sequence. But in the example above if data aren't located in sequential addresses, then the CPU will have to wait for the latency: 5 clock cycles for the first data, 5 clock cycles for the second data and so on. So for random memory accesses lower latency is better. I attached a chart from a DDR2 datasheet from Micron that shows the time table for a DDR2 memory, after the above explanations you will understand it. Cheers, Gabriel. | ||||
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| #12 | |
| Junior Member Join Date: Jan 2008 Posts: 25 ![]() | Hi Gabriel! I wonder something. When the data is written in sequential addresses, so it can be read without latency? Is that up to the software? And why not all of the data (when it's possible) is written sequentially? or is it? Thx in advance. |
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