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Old 12-02-2004, 03:02 PM   #1
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Default The HyperTransport Bus of the Athlon 64

There has been a new article posted.

Title: The HyperTransport Bus of the Athlon 64
URL: http://www.hardwaresecrets.com/article.php?id=19

Here's a snippet:
One of the main differences between the Athlon 64 and 64 FX processors and all the other processors in the market today is that they have an internal circuit called memory controller. In the other processors there is no such circuit, and it is the chipset of the motherboard (more specifically, a circuit called north bridge) that performs the communication ...

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Old 02-14-2006, 05:11 AM   #2
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<quote>The HyperTransport bus works at 3,200 MB/s in each direction (as it was explained, this bus uses one transmission path independent from the reception path) and that is why it is listed as being a 6,400 MB/s bus, which is not true and is one of the main misunderstandings published in the market. In brief, it is as if we said that a highway has a speed limit of 130 MPH just because there is a speed limit of 65 MPH in each direction.</quote>

you are making the common mistake of confusing "speed" aka "latency" with "throughput". their statement is absolutely true, you are just misunderstanding what they are saying.

to take your mixed metaphore to it's rediculous extreme, you are effectively saying "a 1 lane 1 way street with a 65 MPH speedlimit is just as fast as an 8 lane 2 way superhighway with a 65 MPH speedlimit"

yes, it's just as fast, FOR ONE CAR. but if you have any traffic at all, or any need for bi-directional traffic, the one lane road is not useful.

to put it back in computer terms, on an empty bus, the time (latency) to transmit one packet of data in one direction is the same between the both the unidirectional and bi-directional bus, but the maximum bi-directional throughput differs greatly.

their max throughput numbers are absolutely correct.
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Old 09-05-2007, 05:30 PM   #3
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Default AMD processors use HT2.0

“We will be implementing HyperTransport 2.0 technology in a range of AMD Opteron and AMD Athlon 64 processors, starting with the AMD Athlon 64 processors 3000+ and 3200+, which are available today."October 22, 2004
The first 1000MHz HT was a 1.0# (1.03 or 1.05) revision. From October 2004, AMD started shipping parts compatible with the HT2.0 spec at the lower 1000MHz speed (instead of 1400MHz which required additional electronics to filter and compensate).
Documentation from AMD and the HyperTransport consortium doesn't provide enough detail of the transistion to the HT2.0 spec. The marketing & PR department didn't think it mattered when you just hype the GB/s.

* Nvidia nForce5 chipset;
* ServerWorks HT-2000 HyperTransport™ SystemI/O™ Controller from Broadcom Corporation;
* SiS756 HyperTransport to PCI-E/MuTIOL North Bridge;
* AMD-8132™ HyperTransport™ PCI-X® 2.0 Tunnel from AMD;
And many others use the HT2.0 spec.

From the Wiki
HyperTransport is used, with a speed of 800 MHz (Socket 754, one OEM-only Socket 939, older Socket 940, Socket S1, Socket AM2 Semprons) or 1 GHz (almost all Socket 939, newer Socket 940, Socket AM2 Athlons).
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Old 09-07-2007, 06:08 AM   #4
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Hi there,

Yes, I made a huge mistake stating that AMD processors don't use HT2. I will fix this ASAP. I am studying more about this stuff. Please hold on. And thanks a lot for pointing this out to me.

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Old 09-19-2007, 06:25 AM   #5
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Just to let you guys know that I've just updated our HyperTransport tutorial correcting some mistakes I wrote. Basically, I've said HyperTransport 2.0 was never used on AMD CPUs, which is quite wrong -- all current AMD CPUs are based on HT2 using, however, the lower speed grade provided by this version of HyperTransport. It is just that AMD does not say anything about the HyperTransport version they use on their datasheets, what got me confused.
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Old 01-14-2010, 04:10 PM   #6
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Default Re: Errors in understanding of HT and FSB buses


You should have also acknowledged gonar's post, as he has the correct understanding of the difference between the FSB type interface and the HT type. Your explanation and understanding are just wrong. If you wanted to take the part of your understanding that is correct, you would say that single data latency is related directly to the unidirectional speed, but the throughput of the HT is more than twice the speed of a bidirectional single bus of the same speed, because the time required to reverse the bus must be considered. Also, the queuing and dequeuing of the stacked requests must be considered. Separate uni-directional buses are far more efficient than just the twice as much data throughput that is implied by adding their throughputs. The single bi-directional bus will appear more efficient because it will almost always be fully occupied, while the write bus in a pair of uni-directional buses will seldom be as occupied as the read bus, but the capacity is there, and the read bus operates much more efficiently in throughput than it would in a bi-directional mode. If you have not understood this marked difference, you need to review your architecture understanding and do some actual testing of actual throughput on the HT buses. Every one that I have seen shows that HT buses of the same speed and width of FSB's have much greater throughput for separate read and write tests. To test combined throughput, you need to maximize both separately, because few applications will have a one-to-one read/write ration. Though it is simplistic, the memory copy function comes close, though in-cache and out of cache tests will have radically different results. Effectively turning the cache off will produce a result somewhat based on HT or FSB speed, but only roughly. What it really measures is CPU stall and reload speed, which is not exactly the same thing. Pulling the two apart is rather difficult, but can be done. Executing an L1 only test that causes stalls at the same rate of the memory access can then be subtracted from the direct memory access copy without cache, but may not max out the interface. Given all that, the best you are going to get is a "system" rate based on the CPU and bus combination. Fully isolating the bus just is not possible in any way that I can see.
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