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Old 03-17-2008, 11:38 AM   #1
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Default Details on the Forthcoming Intel Nehalem Processor

There has been a new article posted.

Title: Details on the Forthcoming Intel Nehalem Processor
URL: http://www.hardwaresecrets.com/article/535

Here is a snippet:
"Intel released today more details on their forthcoming Nehalem processor, which should arrive on the market by the end of this year. Main features will include a triple-channel integrated memory contr..."

Comments on this article are welcome.

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Old 03-18-2008, 08:09 AM   #2
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its about time intel got an on die memory controller but this should be an awsome performer, it will be my next upgrade I am pretty sure.
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Old 03-19-2008, 04:47 AM   #3
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Talking L3 cache for Intels as well

Finally, my question in the other forum on the K10 architecture has been answered. Intel will also use an L3 cache. Save for the Core architecture, which has proven itself beyond the reach of the AMD's K8, would it be safe to say that Intel has seen the advantages of AMD's designs? Look at the similarities:
  1. On-die memory controller
  2. QuickPath
  3. L3 cache
  4. Separate L2 cache per core

I would like to think that AMD could put up more of a fight against Intel when they start with their Shanghai process. This would surely benefit the end-users!
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Old 05-26-2010, 11:43 AM   #4
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Default Misprint in the article

Gabriel,

in the last paragraph, on page 5, You wrote "The embedded power control unit can now switch off any of the CPU cores, feature not available on mobile Core 2 CPUs". I think that it is a misprint, because on “Figure 5: Nehalem microarchitecture genealogy tree” (page 4) it is said that Core 2 CPUs received “Addition of power management C6 state (on mobile 45 nm models only)”, and You also wrote “Refer to Figure 5 to understand the genealogy of the new Nehalem microarchitecture. We also added the main improvements brought by each new CPU; each CPU has everything brought by the previous CPU plus the mentioned improvements”.

Thank You for the article.
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Old 06-01-2010, 04:56 PM   #5
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Quote:
Originally Posted by paladin2006 View Post
Gabriel,

in the last paragraph, on page 5, You wrote "The embedded power control unit can now switch off any of the CPU cores, feature not available on mobile Core 2 CPUs". I think that it is a misprint, because on “Figure 5: Nehalem microarchitecture genealogy tree” (page 4) it is said that Core 2 CPUs received “Addition of power management C6 state (on mobile 45 nm models only)”, and You also wrote “Refer to Figure 5 to understand the genealogy of the new Nehalem microarchitecture. We also added the main improvements brought by each new CPU; each CPU has everything brought by the previous CPU plus the mentioned improvements”.

Thank You for the article.
Thanks for the feedback. The information is right, you are mixing the C6 state with this feature available to shut down cores (which is NOT the C6 state). Please read this other page for further info:

http://www.hardwaresecrets.com/artic...ng-Modes/611/6

Cheers,
Gabriel.
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