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Old 06-13-2006, 04:13 AM   #1
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Default Understanding RAM Timings

There has been a new article posted.

Title: Understanding RAM Timings
URL: http://www.hardwaresecrets.com/article/26

Here is a snippet:
"DDR and DDR2 memories are classified according to the maximum speed at which they can work. But, besides the speed, there is another information that tells you the memory performance: timings. Timings..."

Comments on this article are welcome.

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Last edited by Gabriel Torres; 06-13-2006 at 04:18 PM.
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Old 06-13-2006, 10:20 AM   #2
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"Thus the period of each clock cycle of a DDR2-533 memory running at 533 MHz (266.66 MHz clock) would be 3.75 ms. Keep in mind that you need to use the real clock rate, which is half the labeled clock rate. So this DDR2-533 memory would delay 18.75 ms to start delivering data, if it had CL =5, or 11.25 ms, if it had CL =3, for example."

Have you forget the prefix "Million Hz" i think you shall calculate again. I am confused. If its true that you telling me shall the RAM access time be like a new HDD.?!
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Old 06-13-2006, 04:17 PM   #3
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Ops, typo! Fixed. The correct unit is ns (nanosecond).

Cheers,
Gabriel.
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Old 09-24-2008, 07:38 AM   #4
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Great tutorial,well done!
I have just one question.When I want to calculate waths the best for my system performance I know I need to use formula T=1/f to get cycle time in nanoseconds,but do I need to multiple it just with CL to get delay or I need to add all timings(CL,tRCD,tRP,tRAS),for example 2.5+3+3+7=15.5 and then multiple 15.5 with cycle time?Or something else?
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Old 09-30-2008, 03:09 PM   #5
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Just CL.

CL, CAS Latency, is what was used to be called "access time". It measures the time the memory delays between receiveing the command from the memory controller and return the requested data.

See the figure below for a better understanding.

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Old 04-13-2011, 05:20 AM   #6
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Quote:
After an ”Active“ command is issued, another ”Precharge“ command cannot be issued until tRAS has been elapsed.
How can Precharge be issued if after "Active" comes tRCD? Why do we need tRAS? Is this a session given between "Active" and "Read/Write"? Memory is giving session like it knows how many clock cycles it will take between "Active" and "Read/Write"?

Can clock cycles be measured in Hertz?

CL=5Hz

Would this be correct?

Last edited by Borisyo; 04-13-2011 at 07:42 AM.
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Old 04-14-2011, 10:40 AM   #7
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CL is measured in clock cycles, not in Hz.
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Old 04-14-2011, 02:47 PM   #8
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Question

According to this article from Wikipedia, clock cycle is same as Hertz.

Quote:
As mentioned before, CAS Latency (CL) is the most famous memory parameter. It tells us how many clock cycles the memory will delay to return a requested data.
So if we have DDR2-533 with delay of 5 clock cycles, lets assume it is working constantly and effectively on 533Mhz and has permanent 5 Hertz latency (5 clock cycles), divide 533000000Hertz by 5Hertz and we get 106600000Hertz or 106Mhz theoretically making it to receiving instructions and returning data at 106Mhz.

Last edited by Borisyo; 04-14-2011 at 02:50 PM.
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Old 04-14-2011, 10:53 PM   #9
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Quote:
Originally Posted by Borisyo View Post
According to this article from Wikipedia, clock cycle is same as Hertz.
No it doesn't state that! Just as Gabe says it states the number of actual cycles it's delayed.

Quote:
Originally Posted by Borisyo View Post
... divide 533000000Hertz by 5Hertz and we get 106600000Hertz
No you don't! If you divide hertz with hertz you get no unit at all!
CL is a unit-less number, so divide 1 by [hertz] and you get [seconds].

CL 5, as used in your example, means there's a delay of
5 x 1/533,000,000 seconds = 9.4 ns
to answer each request for data.

Hope this helps...
Olle
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Old 04-15-2011, 01:33 AM   #10
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Quote:
Originally Posted by Olle P View Post
No it doesn't state that! Just as Gabe says it states the number of actual cycles it's delayed.
"The hertz is equivalent to cycles per second" - this is what said in Wikipedia.

Quote:
Originally Posted by Olle P View Post
No you don't! If you divide hertz with hertz you get no unit at all!
CL is a unit-less number, so divide 1 by [hertz] and you get [seconds].

CL 5, as used in your example, means there's a delay of
5 x 1/533,000,000 seconds = 9.4 ns
to answer each request for data.

Hope this helps...
Olle
So memory still works at DDR 533MHz but it just delays response? Okay but when determining that DDR 533Mhz or clock cycles we do not take into account 5 clock cycles of latency? I mean if there was CL=0 then memory would work at exactly DDR 533Mhz right?

If processor works at 3Ghz, does it have latency like memory does?
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