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Old 08-25-2008, 09:56 AM   #1
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Default Everything You Need to Know About The QuickPath Interconnect (QPI)

There has been a new article posted.

Title: Everything You Need to Know About The QuickPath Interconnect (QPI)
URL: http://www.hardwaresecrets.com/article/610

Here is a snippet:
"Since the beginning of times Intel CPUs use an external bus called Front Side Bus or simply FSB that is shared between memory and I/O requests. The next generation of Intel CPUs will have an embedded ..."

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Old 11-02-2008, 09:42 AM   #2
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how come that some Core i7 CPU's are rated to 4.8GT/s when the article states that the first version of the QPI will run at 6.4GT/s ??
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Old 12-01-2010, 09:35 PM   #3
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Hi to all

This is about some doubts that the QuickPath Interconnect makes me wonder.'

With the inclusion of the MCC into the CPU die, the FSB does not exist anymore.

But the FSB should still exist internally as a connection CPU - data bus + address bus - MCC, and leaving outside the memory bus as it was before. (Now serial)

The main reason for the appearance of the AGP bus was to give to the graphics inputs its own bus, totally separated of the general I\O bus, given birth to the South Bridge (maybe I am not totally accurate, but I think the idea still does)

Now with the coming of the QPI, the graphics bus (AGP\PCIe) got back to the South Bridge and to the shared I\O bus.

It is not a step backwards?

Its solves the problem the serial connection of the QPI?

And now with QPI, Which is the "master" bus, I mean, from which bus-clock are derived all the other clock rates or speeds?
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Old 12-06-2010, 03:59 PM   #4
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Quote:
Originally Posted by kbhadsten View Post
how come that some Core i7 CPU's are rated to 4.8GT/s when the article states that the first version of the QPI will run at 6.4GT/s ??
This is the kind of problem that happens when we write a tutorial before the actual product is around. It should read "up to" in the tutorial. I will fix this whenever I have the time.

Quote:
Originally Posted by Richardo51 View Post
Hi to all

This is about some doubts that the QuickPath Interconnect makes me wonder.'

With the inclusion of the MCC into the CPU die, the FSB does not exist anymore.
Yes.

Quote:
Originally Posted by Richardo51 View Post
But the FSB should still exist internally as a connection CPU - data bus + address bus - MCC, and leaving outside the memory bus as it was before. (Now serial)
No.

Quote:
Originally Posted by Richardo51 View Post
The main reason for the appearance of the AGP bus was to give to the graphics inputs its own bus, totally separated of the general I\O bus, given birth to the South Bridge (maybe I am not totally accurate, but I think the idea still does)

Now with the coming of the QPI, the graphics bus (AGP\PCIe) got back to the South Bridge and to the shared I\O bus.

It is not a step backwards?
No, because the PCI Express is not a bus, but a point-to-point connection. Bus in the strict sense is shared by all devices connected to it, for example, that is what happens with the old PCI and ISA busses. The PCI Express is a point-to-point connection, meaning that only the two devices connected to it can talk.

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Originally Posted by Richardo51 View Post
Its solves the problem the serial connection of the QPI?
There is no "problem" of the QPI being serial, so I don't understand your question.

Quote:
Originally Posted by Richardo51 View Post
And now with QPI, Which is the "master" bus, I mean, from which bus-clock are derived all the other clock rates or speeds?
There is a clock generator on the motherboard that creates a base clock of 133 MHz from which all other clocks are derived from, in most cases. There is no such thing as a "master bus".

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Old 12-06-2010, 06:07 PM   #5
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back when FSB existed everything made sense to me like how it all connected, the frequencies, etc. but this QPI **** is confusing. (no i didnt read the article, thats part of the problem i think)...:P
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Old 12-07-2010, 11:35 AM   #6
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Thanks for your answer Gabriel as always.

Well first to say that my question is kinda of out-of-place, because at the same time I said the "serial" connection (that I mean is point-to-point, I believe they were the same ..), so being point-to-point, evidently, there is not "sharing" connection, yes, AGP\PCIe aren't buses (I should read\write slowly .. )

And about what I meant with the problem with the "serial" QPI (read point-to-point) is that, is this connection fast enough to absorb all the traffic coming from the rest of the devices\buses? There is not bottleneck? (evidently it shouldn't, as FSB it was already doing the job before... )

The same about my quote or the FSB, just looking the picture is clear that FSB is not there anymore, memory has its own dedicated channel.

By the way, Gabriel, your quote:

"This is the kind of problem that happens when we write a tutorial before the actual product is around. It should read "up to" in the tutorial. I will fix this whenever I have the time."

I do not know what exactly you meant, but for me the tutorial, as all of the others I read from you, is excellent and crystal clear, yes I got my doubts and confusions (training CompTia A+) but I don't think is the tutorial exactly.

Thanks for your time.

Ricardo
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Old 12-07-2010, 03:21 PM   #7
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Quote:
Originally Posted by Richardo51 View Post
And about what I meant with the problem with the "serial" QPI (read point-to-point) is that, is this connection fast enough to absorb all the traffic coming from the rest of the devices\buses? There is not bottleneck? (evidently it shouldn't, as FSB it was already doing the job before... )
This kind of circuit has always a buffer to absorb traffic peaks, if they happen.

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By the way, Gabriel, your quote:
This was an answer to the question the other user posted above.

I hope I have helped.

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Old 12-08-2010, 04:51 PM   #8
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Quote:
Originally Posted by Gabriel Torres View Post
This kind of circuit has always a buffer to absorb traffic peaks, if they happen.



This was an answer to the question the other user posted above.

I hope I have helped.

Cheers,
Gabriel.

Yes you did.

Thanks.
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